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Inverter Switching and Average Model, by Vinod John

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Inverting Amplifier, by Nagendra Krishnapura

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Ion-Implantation Process, by Nandita Dasgupta

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Islanding of Distribution Systems, by Vinod John

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Isolated Converters – II, by V. Ramanarayanan

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Isolated Converters-I, by V. Ramanarayanan

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Issues Related to Switches, by V. Ramanarayanan

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J-K and T Flip Flops, by S. Srinivasan

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K-Map Minimization, by Shankar Balachandran

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K-Map with Don’t Cares, by Shankar Balachandran

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K-Stage Pipeline, by Shankar Balachandran

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Karnaugh Map Minimization Using Maxterms, by S. Srinivasan

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Karnaugh Maps and Implicants, by S. Srinivasan

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Karnaugh Maps, by Shankar Balachandran

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KCL with an Opamp and Supply Currents, by Nagendra Krishnapura

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KCL, KVL & Network Analysis, by S.C. Dutta Roy

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Kirchhoff’s Current Law (KCL), by Nagendra Krishnapura

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Kirchhoff’s Voltage Law (KVL), by Nagendra Krishnapura

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L1-Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design, by Virendra Singh

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L10-Arithmetic Implementation Strategies for VLSI, by Virendra Singh

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L11-Arithmetic Implementation Strategies for VLSI-Part II, by Virendra Singh

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L12-Arithmetic Implementation Strategies for VLSI-Part III, by Virendra Singh

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L13-Arithmetic Implementation Strategies for VLSI-Part IV, by Virendra Singh

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L14-Interconnect Aware Design: Impact of Scaling, Buffer Insertion and Inductive Peaking, by Virendra Singh

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L15-Interconnect Aware Design: Low Swing and Current Mode Signaling, by Virendra Singh

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L16-Interconnect Aware Design: Capacitively Coupled Interconnects, by Virendra Singh

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L17-Introduction to Hardware Description Languages, by Virendra Singh

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L18-Managing Concurrency and Time in Hardware Description Languages, by Virendra Singh

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L19-Introduction to VHDL, by Virendra Singh

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L2-Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design-Part II, by Virendra Singh

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L20-Basic Components in VHDL, by Virendra Singh

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L21-Structural Description in VHDL, by Virendra Singh

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L22-Behavioral Description in VHDL, by Virendra Singh

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L23-Introduction to Verilog, by Virendra Singh

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L24-FSM + Datapath (GCD Example), by Virendra Singh

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L25-FSM + Datapath (Continued), by Virendra Singh

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L26-Single Cycle MMIPS, by Virendra Singh

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L27-Multicycle MMIPS, by Virendra Singh

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L28-Multicycle MMIPS – FSM, by Virendra Singh

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L29-Brief Overview of Basic VLSI Design Automation Concepts, by Virendra Singh

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L3-Logical Effort-A Way of Designing Fast CMOS Circuits, by Virendra Singh

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L30-Netlist and System Partitioning, by Virendra Singh

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L31-Timing Analysis in the Context of Physical Design Automation, by Virendra Singh

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L32-Placement Algorithm, by Virendra Singh

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L33-Introduction to VLSI Testing, by Virendra Singh

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L34-VLSI Test Basics-I, by Virendra Singh

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L35-VLSI Test Basics-II, by Virendra Singh

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L36-VLSI Testing: Automatic Test Pattern Generation, by Virendra Singh

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L37-VLSI Testing: Design for Test (DFT), by Virendra Singh

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L38-VLSI Testing: Built-In Self-Test (BIST), by Virendra Singh

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